To enhance the performance of Metal-Oxide-Semiconductor (MOS) devices, stress may be introduced in the channel regions of the MOS devices to improve carrier mobility. Generally, it is desirable to induce a tensile stress in the channel region of an N-type MOS (“NMOS”) device in a source-to-drain direction of the NMOS device, and to induce a compressive stress in the channel region of a p-type MOS (“PMOS”) device in a source-to-drain direction of the PMOS device.
A commonly used method for applying compressive stresses to the channel regions of PMOS devices is growing SiGe stressors in the source and drain regions of the of the PMOS devices. Such a method typically includes the steps of forming a gate stack on a silicon substrate, forming spacers on sidewalls of the gate stack, forming recesses in the silicon substrate and adjacent to the gate spacers, and epitaxially growing SiGe stressors in the recesses. An annealing is then performed. Since SiGe has a greater lattice constant than silicon, it expands after annealing and applies a compressive stress to the channel region of the respective MOS device, which is located between a source SiGe stressor and a drain SiGe stressor.